Statement of Work

Semiconductor Electrical Modeling for In-Space Memory Manufacturing

Principle Investigator: Electrical and Computer Engineering, Arizona State University

Duration: May 2023 – March 2024

Project Overview:

With the increasing demand of computing, in-space memory manufacture enables the rapid prototyping and open the era of semiconductor chips manufactures High efficient, low cost and high functionality of chips manufactured in the zero-G environment through the inkjet printing process. Printing manufacturing is also useful for fabrication of high-density memory as three-dimensional design. These features are critical for NASA missions. Achieving high accuracy and resolution are the major challenges in improving the printing quality. As emerging printing device and evaluation methods are being invented, defect and failure model also need to be developed to maximize the printable semiconductor device technology.

Our lab has developed a memory electrical-materials characterization methodology for evaluating the thin-film memory by printing technology. Our preliminary data has the current-voltage (I-V) characteristics, time-dependent speed evaluation (~ns), and numerical fitting for current transport mechanisms understanding. In addition, the radiation effect on thin-film memory window and switching performance were investigated in our preliminary results. We propose to work closely with Intel and NASA Marshall Space Flight Center (MSFC) On-Demand Manufacturing of Electronics (ODME) systems, Space enable advanced device and semiconductor (SEADS). The objective is to conclude the groundwork with PVD thin film evaluation and device characterization to support the preliminary results for flight test scheduled in August 2023. We will characterize the performance and reliability for printed memory in our lab by DC/AC measurement, accelerated failure industrial test, and temperature-accelerated retention failure, after the test flight bringing back the devices. Besides, device and fabrication process will be optimized by materials analysis results with KLA Tencor Profilometer, four-point probe, scanning electron microscopy (SEM), and transmission electron microscopy (TEM) at ASU, before the test flight in August.

Semiconductor device properties, especially the electrical characteristics and thin film deposited on the patterned wafer with sub-micron trenches, will be tailored to help optimizing the memory structures and design. Based on benchmarking the current transport and defect in devices, the process can be advanced to the future oxide-based transistor-memory integration co-design.